Intel’s 14nm Broadwell chip reverse engineered, reveals impressive FinFETs, 13-layer design
Intel stated that it would bring 14nm in with substantial scaling in transistor fin pitch, transistor gate pitch, and interconnect pitch, with a further significant reduction in SRAM scaling. Now, independent analysis and reverse engineering from Chipworks has confirmed that Intel did indeed deliver on its technological promises. Gate pitch has been measured at ~70nm, fin pitch at ~42nm, and a more complex 13-layer metal design. Intel had previously stuck with nine-layer designs before stepping up to 11 for its Bay Trail SoC.When Intel announced the details on its 14nm process last year, it raised eyebrows in some circles by claiming some extremely aggressive scaling figures. Put simply, Intel stated that it would deliver a better 14nm process with superior characteristics, die size, and overall efficiency than any competitive product TSMC, its largest foundry competitor, would release on 20nm. This predictably kicked off a PR blizzard between the two companies. The FinFET t